1. Field of the Invention
This invention is related to the field of processors and, more particularly, to data prefetching mechanisms in processors.
2. Description of the Related Art
Memory latencies are now a dominant factor in modern processor performance. As processor speeds have increased over the years, memory speeds have failed to keep pace. As a result, memory latencies have increased when measured in terms of numbers of processor clock cycles. Various strategies are being employed to mitigate the impact of these increased latencies. Some of these strategies include various forms of multi-threading (allowing other threads to continue while one thread waits for memory), larger caches, and various forms of speculation including run-ahead execution and result prediction.
Data prefetching can be used to alleviate performance lost to memory latency. Data prefetchers analyze a set of memory accesses, attempting to predict patterns within those accesses. When a pattern is recognized, prefetches can be issued to begin retrieving data from memory ahead of when the program requires it.
Prefetches can also interfere with the “real” accesses generated directly from instruction execution (often referred to as demand fetches or demand accesses). Accordingly, generating accurate prefetches (i.e. prefetches that have high likelihood of being the target of demand accesses that occur in later instruction execution) is important. A prefetcher that generates significant numbers of inaccurate prefetches can reduce performance.